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Summit M5x Protocol Analyser/Jammer

Summit M5x Protocol Analyser/Jammer

The Summit M5x is Teledyne LeCroy's PCIe/ NVMe Jammer solution and is the latest protocol analyzer targeted at high speed PCI Express 4.0 I/O-based applications such as workstation, desktop, graphics, storage, and network card applications.

The Summit M5x Protocol Analyzer /Jammer is the computer industry’s first platform to not only support today’s PCIe 4.0 specification but is designed to also support the next generation PCIe 5.0 (32GT/s) specification and introduces new error injection (jamming) capabilities for PCIe testing in addition to high speed recording and analyzing. The Summit M5x protocol analyzer/jammer features the PCIe industry’s first PCIe 4.0 compliant specification jamming test capability.

The Summit M5x platform is PCIe 5.0 ready and will support up to 32 GT/s transmission speeds. Monitoring and analyzing other high-speed protocols that leverage the PCIe electrical specification but may run at other speeds using their own protocols such as GenZ and CCIX will also be possible in the future on this analysis platform. Summit M5x users who are using PCIe 4.0 today can upgrade to PCIe 5.0 by purchasing a software license upgrade along with any necessary probes that they may need for their environment.

Summit M5x introduces a new probing methodology that eliminates the need of a traditional “interposer” type probe to interface with systems under test. This is ideal for server based systems that utilize horizonal insertion. The Summit M5x supports PCIe 4.0 at up to x16 link widths its memory buffer can be configured up to 128GB, which is advantageous for users requiring long protocol recordings. The protocol analyzer can be controlled through USB or remotely through 1000baseT Ethernet. The Summit M5x protocol analyzer can also be synchronized with other high-speed protocol analyzers from Teledyne LeCroy using CrossSync, functionality that enables time‐aligned packet traffic as well as cross triggering from multiple high‐speed serial busses as may be needed to design, debug and validate across bridges.

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