Top of page Skip navigation
XJTAG Boundary Scan
XJTAG Boundary Scan


XJ Link

JTAG Boundary Scan Workshop

Registration Form

XJTAG workshop banner

This full-day session is designed to provide design, development, test, and production engineers with a practical hands-on introduction to boundary scan.

With hardware becoming increasing complex, and BGA devices even smaller and harder to access, boundary scan has become an essential part of the design process for many engineers.

Find out how boundary scan can be used right across the product lifecycle to improve designs, reduce respins and enhance test coverage, fault diagnosis and production yields on complex hardware. The workshops outline the following:

  • Overview of the IEEE 1149.x standards
  • How to communicate with the JTAG chain
  • Tools to interact with JTAG devices, such as FPGAs or BGAs
  • Introduction to board testing using the JTAG chain
  • How to describe a circuit in order to enable JTAG testing
  • Fault finding abilities of a JTAG connection test
  • How to test non-JTAG elements of a board design using boundary scan

Dates for 2018:

  • Thursday 8th March 2018, Cambridge, UK
  • Thursday 21st June 2018, Cambridge, UK

Cost: Free of charge including free lunch.

If you would like to attend the workshop please fill in the registration form below, including your preferred date(s) and location:

Please complete all mandatory fields marked *
Title *
First name *
Last name *
Email address *
Company *