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PCI Express Seminar

PCI Express Seminar

8 October 2020

Join us for a free 1 day seminar where Teledyne LeCroy will be sharing the techniques used for the validating and debugging of PCI Express based designs with the use of PCI protocol analysers.  Plus have the opportunity to bring along your PCI Express device card to run against the Teledyne LeCroy compliance platform as used at the PCI-SIG compliance workshops for Link and Transaction testing.




The seminar will focus on a number of key aspects of PCI Express design, highlighting the issues which can be encountered and techniques for identifying and resolving these issues.

Primary focus areas will be:

1)  Link establishment:  Examining the process by which a PCIe link is established through link training.  How to identify when the expected link widths or data rates are not achieved and the causes.

2)  Link performance: Looking at the symptoms and causes of reduced link performance when the desired link data rate and width have been established. Understanding issues at the Data Link Layer such as, Flow Control starvation, Active State Power Management etc.

3) Application errors: Applications running over the PCIe link directly effect the behaviour of system. How the view provided by a protocol analyser can be the fastest way to identifying application errors

4) Compliance: What is PCIe compliance?  Do I need compliance?  How do I go about performing compliance on my device/host?

5) New jamming techniques: Changes in the 4.0 PCIe specification relaxing the Replay Timer requirements now means that PCIe compliant jamming is now possible.  With the ability to dynamically modify traffic on all layers of an active PCIe link a whole new set of techniques can be employed for confirming how a device or host handles specific errors or bus conditions.   

6) Differences between PCIe 3.0, 4.0 & 5.0 specifications: What are the key differences between the specifications.  Why should I care about the 4.0 or 5.0 specification if my implementation is only going to run at Gen3?

As the leaders in PCI Express protocol analysis and compliance testing since 2004, Teledyne LeCroy have a vast amount of experience in this area.  Experience gained from not just the design of the protocol analyser, exerciser and jamming products but also from the use of this equipment with a large client base.  The seminar is an opportunity for engineers to tap into this knowledge.

We will also have a guest speaker from the Intel sharing their insights into debugging platforms utilising Teledyne LeCroy protocol analysers to observe behaviour on the PCIe bus.

If you wish to bring along your PCIe device card to run against the Teledyne LeCroy compliance platform you will need to provide details in advance of the seminar.  Please state in the comments field of the registration form your intention to bring along your device card and we will contact you to confirm details. No third party device cards will be eligible.

Location: Maidenhead, UK. Lunch and refreshments included.

Please note that due to the popularity of these events we have to restrict the number of places per company to two attendees on a first come first served basis.

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