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J-Testr functional testing
J-Testr functional testing

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Functional and power testing of high-value hardware workshop

 

Modern hardware often has high-value FPGA and / or SOC devices onboard and require multiple point-of-load power supplies with significant variation in current demand during product operation. Power is the oxygen of any electronic system and requires proper testing to avoid reliability issues and / or early life failures. This testing is often neglected due to the complexity of implementation and space required when using conventional test systems, which often use discrete & bulky power supplies and electronic loads. Cabling considerations such as voltage drop and noise pick-up adds further complication.

The J-Testr universal functional test system provides all the common analogue and digital test stimulation & measurement features required, but unlike other functional test systems on the market, the J-Testr has also been designed with proper power testing in mind. It provides high performance modular plug-in power supply and electronic load ‘peripheral cards’ all within the compact system size. The unique ‘direct’ interposer plugging connection system of the J-Testr greatly simplifies wiring complexity and length, and helps dramatically reduce voltage drop and noise pick-up issues.  Advanced features such as digital ramp rate and sequencing control allow the simulation & testing of almost any ‘worse case’ specified supply sequence, ramp & loading conditions, including fast current load transients.

Testing the UUT (Unit Under Test) power supplies correctly is just one of the power issues faced by a test engineering department, but it is arguably the most important issue. Protection and safety of the UUT is paramount, particularly during the first power-up, because a simple production fault on a board can easily destroy it before any testing is even started. With the J-Safe system, test engineers are able to setup robust protection strategies to greatly minimise the risk of damage to the UUT during testing, particularly during the first power-up.

Workshop objectives - provide participants with knowledge of:

  • Why thorough power supply testing is a vital part of product functional testing.
  • The power issues that commonly occur and their typical effect on a UUT.
  • Typical power tests (Voltage, Current, Load-regulation, Line-Regulation, and Efficiency).
  • Advanced power tests (Frequency measurement , Ripple measurement, Transient).
  • Implementing both typical and advanced power testing using the J-Testr system (Demo / hands on).
  • Setting up UUT protection strategies using J-Safe (Demo / hands on).
  • General use of the J-Testr system and its debugging tools (Demo / hands on).


Who should attend: Hardware, software and test development engineers who are involved in either product design verification or the production test environments. 

Venue: Maidenhead, UK

Dates: Please contact us for 2018 dates

Cost: First two places per company free of charge (including lunch); additional places chargeable 

If you would like to attend the workshop please fill in the registration form below, including preferred date.

 

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